About APEMC2017


The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium is the premier international conference in Asia-Pacific region to share the recent progress of modeling, simulation and measurement for the electrical design issues on chip, package and system levels. Covering the paper presentations, industry exhibitions, workshops and tutorials, the APEMC2017 will be held in COEX, Seoul, Korea from December 14 to 16, 2015. The technical program of the symposium not only addresses the current technical issues but also brings out the topics on IC design, SiP/SoP packaging, EMI/EMC, EDA tools and most importantly the challenge issues in advanced 3D-IC and TSV design. For further information, please send your inquiry to edaps15@gmail.com


Deadline for Regular Paper Submission August 31, 2015
Acceptance Notification October 5, 2015
Early Bird Due Date November 15, 2015


  • 3D-ICs / TSVs / Interposers
  • Testing on 3D-IC and SiP
  • Signal and Thermal Integrity
  • Power Integrity / Power Distribution Networks (PDNs) / Ground Noise
  • Multi-physics Simulation Techniques for SI / PI / TI Analysis
  • Design and Modeling for High-speed Channels and Interconnects
  • Time / Frequency Domain Measurement Techniques
  • Electronic Packages, SiP / SoP
  • IC and Package Level EMC
  • RF/mm-wave Packages
  • Embedded Passives
  • Power Electronic Packages
  • Advanced Simulation Tools and CAD
  • Substrate Technology for Packages and PCBs
  • Package Reliability
  • Others